Apparatus and methods for plug fill deposition in 3-D NAND applications

ABSTRACT

An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a nonprovisional of, and claims priority to and the benefit of, U.S. Provisional Patent Application Ser. No. 62/807,989, filed Feb. 20, 2019 and entitled, “APPARATUS AND METHODS FOR PLUG FILL DEPOSITION IN 3-D NAND APPLICATIONS,” which is hereby incorporated by reference.

FIELD OF INVENTION

The present disclosure generally relates to an apparatus and methods for forming Not-AND (NAND) Devices. More particularly, the disclosure relates to deposition of a plug fill for a 3-D NAND device made in part of oxide-nitride layer stacks. The apparatus and method for forming the NAND devices may include use of a sacrificial material and fabrication scheme to achieve proper formation of device structures at lower cost and higher throughput.

BACKGROUND OF THE DISCLOSURE

NAND devices are logic gates usable in applications such as flash memory, for example. Manufacture of the NAND devices may include formation of a channel hole in layers disposed on a substrate. The channel hole then may be filled with a sacrificial material, and then removed. An example of a process manufacturing a NAND device 100 is illustrated in FIGS. 1A-1D. The NAND device 100 may comprise a substrate 110, a nitride layer 120, and an oxide layer 130. Deposition of the nitride layer 120 and the oxide layer 130 is repeated as needed to form a stack.

As shown in FIG. 1A, the NAND device 100 comprises a first stack 140 comprising an alternation of two nitride layers 120 and two oxide layers 130. The NAND device 100 also comprises a second stack 150 comprising an alternation of two nitride layers 120 and two oxide layers 130. The first stack 140 and the second stack 150 may comprise additional alternations of the nitride layer 120 and the oxide layer 130.

The nitride layers 120 and the oxide layers 130 undergo an etch process to form a channel hole, as shown in FIG. 1B. The etch process may involve an oxide or nitride dry etch chemistry with fluorine based such as NF3, CHF, SF6, CF4 and their mixtures. The dry etch chemistry may involve oxygen or ozone in some cases. FIG. 1C illustrates the NAND device 100 after undergoing a first process to form a liner after the dry etch process to form called Channel Holes or Memory Holes, a second process to form a plug fill, and a third polishing process. The NAND device 100 then comprises a liner 160 and a plug fill 170. The liner 160 may comprise silicon oxide (SiO_(x)), for example.

The plug fill 170 may comprise polysilicon, tungsten (W), titanium nitride (TiN), aluminum oxide (AlO_(x)), metal carbides, tungsten carbide (WC), tungsten borocarbide (WBC), metal nitrides, or a combination of any listed above. Depending on the material used for the plug fill 170, there may be increased cost and a greater risk of instability due to failure as it relates to integration. The plug fill 170 may comprise a sacrificial material used to protect a channel hole or a memory hole at the bottom of the stack 140. A cap (not illustrated) may also be optionally disposed on top of the plug fill 170. The cap may comprise a metal nitride, such as titanium nitride, tungsten nitride, or aluminum nitride, for example.

The third polishing process may be chemical mechanical polishing (CMP). After the third polishing process, additional oxide-nitride layer stacks may be added on top of the stack 150, the liner 160, and the plug fill 170.

However, it may come to a point that after the channel hole is filled with the liner 160 and the plug fill 170, the liner 160 and the plug fill 170 has to be removed in its role as a sacrificial material. The plug fill 170 may be removed with a wet etch process using at least one of: ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂), water (H₂O), NHO₃, TDMH, or a combination of the foregoing. The plug fill 170 may be removed by a dry etch using a halide chemistry, such as hydrofluoric acid (HF), hydrochloric acid (HCl), or hydrobromic acid (HBr), for example. A wet clean process may follow with HF mixture to remove the liner (160).

FIG. 1D illustrates the NAND device 100 after the removal takes place. However, the chemistries may leave a residue 180 and/or cause damage 190 to either the nitride layer 120 or the oxide layer 130 by the chemistries used for the removal of liner 160 and/or plug fill 170. The residue 180 and the damage 190 may render the NAND device 100 unusable. In addition, the removal of the liner 160 and the plug fill 170 may be done with a slow etch rate, which means that the time to remove the liner 160 and the plug fill 170 may be undesirably long. This may be the result of the plug fill 170 being formed of a recrystallized silicon or a silicon in a (111) crystallization orientation, for example. The recrystallized silicon may result due to an anneal process when forming an additional stack.

Furthermore, an additional issue that may arise is a misalignment of stacks when the additional stacks are disposed on top of the first stack 140 and the second stack 150. The misalignment may be a result of stresses imposed on the different stacks, the liner 160, and/or the plug fill 170 during manufacture.

As a result, it is desired to achieve an apparatus and a method for forming the NAND device at low cost and high throughput with minimized or no residue and damage in the channel hole and good structural integrity.

SUMMARY OF THE DISCLOSURE

This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In accordance with at least one embodiment of the invention, a method is disclosed, the method comprising a method of forming a 3-D NAND device on a substrate. In various embodiments, the method may comprise: depositing a bilayer structure on a semiconductor substrate, wherein the bilayer structure comprises alternating layers of an oxide layer and a nitride layer; etching a channel hole in the bilayer structure with a first chemical; depositing a liner on a top of the bilayer structure and/or on a side of the bilayer structure within the channel hole; depositing a plug fill in the channel hole, the plug fill comprising a void and at least one of: silicon germanium plug or a graded germanium plug; polishing the plug fill; etching the plug fill with a second chemical; and/or removing the liner; wherein any of the above steps are repeated to form a desired height of the 3-D NAND device.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of certain embodiments, which are intended to illustrate and not to limit the invention.

FIGS. 1A-1D are cross-sectional illustrations of a NAND device formed via a prior art process.

FIGS. 2A-2I are cross-sectional illustrations of a NAND device formed in accordance with at least one embodiment of the invention.

FIG. 3 is a process flow diagram in accordance with at least one embodiment of the invention.

FIG. 4 is a cross-sectional illustration of a NAND device formed in accordance with at least one embodiment of the invention.

It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below.

The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure.

Three-dimensional (3-D) Not-AND (NAND) devices may be utilized in memory applications. The 3-D NAND devices may involve stacks of bilayers disposed on each other. The bilayers may comprise oxides and nitrides, for example. When disposing stacks of multiple bilayers on other stacks, alignment and stresses on the layers and different features may become critical.

FIG. 2A illustrates a 3-D NAND device 200 in accordance with at least one embodiment of the invention. The device 200 comprises a substrate 210, a nitride layer 220, and an oxide layer 230. The substrate 210 may comprise silicon, silicon oxide, and/or a metal oxide. The nitride layer 220 may comprise at least one of: silicon nitride, germanium nitride, silicon germanium nitride (SiGeN), silicon oxynitride (SiON), germanium oxynitride (GeON), or combinations thereof. The oxide layer 230 may comprise at least one of: silicon oxide, germanium oxide, silicon germanium oxide (SiGeOx), germanium oxynitride (GeON), silicon oxynitride (SiON), or combinations thereof.

The device 200 then may go through a process to form a channel hole or memory hole by wet or dry etch process to result in the device 200 shown in FIG. 2B. The dry etch process may utilize a halide chemistry with fluorine based such as NF3, CHF, SF6, CF4, and their mixtures, for example. The dry etch process may involve a remote plasma system, for example. The dry etch chemistry may involve oxygen or ozone in some cases.

Afterwards, a liner 240 may be added to the device 200 as shown in FIG. 2C. The liner 240 may comprise at least one of: germanium oxide, germanium (Ge), silicon germanium (SiGe), germanium nitride (GeN), or pure silicon (Si). The liner 240 may cover the tops and/or the sides of the oxide layer 230/nitride layer 220 bilayer stack. The liner 240 may also extend to cover an exposed portion of the substrate 210. The liner 240 may be deposited via an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, or an epitaxial process, for example.

FIG. 2D illustrates the result after a 3-D plug fill takes place. The device 200 comprises a plug fill 250 and a void 260. The plug fill 250 may comprise at least one of: silicon germanium (SiGe) or a graded germanium. The concentration of germanium in a SiGe plug fill 250 may range between 1% and 100%. The germanium content may be modulated for obtaining desirable material properties needed in the subsequent process steps of 3D NAND, such as removal rate in etch processes and thermal stability, for example.

The shape of the plug fill 250 may be different as well as the size of the void 260 depending on the process used for the 3-D plug fill. As a result of forming the void 260, the plug fill 250 is completely filled or not completely filled, resulting in what is called a void or pinch-off inside the holes. The void or pinch-off may result in a quicker removal during removal of the plug fill 250 later on in the process, thereby reducing the device damage by the etch chemistry and the time to manufacture and increasing throughput. The void or pinch-off may not exist in certain embodiments of the invention.

The plug fill 250 and the void 260 may be formed through an in-situ process comprising a deposition step, an etch back step involving a halide chemistry, and a pinch-off step. The deposition step may occur by a thermal reaction, a plasma reaction, a plasma enhanced reaction, or a high density plasma (HDP) chemical vapor deposition (CVD) process. The deposition step may include flow of a silicon precursor such as silane, disilane, trisilane, chlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, neopentasilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, or a combination of the foregoing, for example. The deposition step may also include a flow of a germanium precursor, such as germane, digermane, dichlorogermane, trichlorogermane, tetrachlorogermane, germanium alkoxide, or a combination of the foregoing, for example. The deposition step may also comprise flowing a precursor containing both silicon and germanium, such as silyl-germane precursors, for example. The deposition step may involve an in-situ doping of germanium. The in-situ doping may be done with atoms such as Ga, B, P, As, or Al.

The in-situ process may comprise a pinch-off step, where the pinch-off step comprises deposition of silicon, germanium, or a combination thereof in order to form the void 260.

For a thermal deposition step, the pressure may range between 10 Torr and 800 Torr, while the temperature may range between 50° C. and 800° C. For a plasma enhanced reaction or HDP CVD deposition step, the pressure may range between 10 mTorr and 100 Torr, while the temperature may range between 10° C. and 700° C.

The halide chemistry involved in the etch back step may comprise hydrofluoric acid (HF), hydrochloric acid (HCl), hydrofluoric acid (HF), hydrobromic acid (HBr), or a combination of the foregoing, for example. The dry etch process may involve a remote plasma system, for example.

The germanium, Silicon or SiGe plug fill and pinch-off step may comprise depositing a SiGe alloy at reduced deposition rate to accurately control the thickness. This step may also create a void in the SiGe alloy. The germanium or Silicon or SiGe plug fill and pinch-off step may be achieved using an apparatus disclosed in U.S. patent application Ser. No. 16/055,532, entitled “MULTI-PORT GAS INJECTION SYSTEM AND REACTOR SYSTEM INCLUDING SAME” and filed on Aug. 6, 2018 by Ma et al., which is hereby incorporated by reference. The germanium, Silicon, SiGe plug fill and pinch-off step may be alternatively achieved using an apparatus disclosed in U.S. patent application Ser. No. 15/997,445, entitled “GAS DISTRIBUTION SYSTEM AND REACTOR SYSTEM INCLUDING SAME” and filed on Jun. 4, 2018 by Sreeram et al., which is hereby incorporated by reference. The apparatus described in these patent applications may allow for an adjustment in the size of the void created.

The excess material of the plug fill 250 may be removed via a CMP process as shown in FIG. 2E. What is left over forms a first stack 270. Once there is a level surface, an additional stack may be formed on the liner 240 and the plug fill 250.

A second stack 280 is shown in FIG. 2F. The second stack 280, like the first stack 270, comprises an alternating arrangement of a nitride layer 220 and an oxide layer 230. The nitride layer 220 may comprise at least one of: silicon nitride, germanium nitride, silicon nitride, germanium nitride, silicon germanium nitride (SiGeN), silicon oxynitride (SiON), germanium oxynitride (GeON), or combination thereof. The oxide layer 230 may comprise at least one of: silicon oxide, germanium oxide, silicon germanium oxide (SiGeOx), germanium oxynitride (GeON), silicon oxynitride (SiON), or combination thereof.

A channel hole is then formed in the second stack 280 via an etch process. The etch process may be a dry etch or a wet etch process. The etch process may utilize a halide chemistry, such as hydrofluoric acid (HF), hydrochloric acid (HCl), hydrofluoric acid (HF), or hydrobromic acid (HBr), or a combination of the foregoing, for example. The liner 240 and the plug fill 250 remain left over after the etch process as shown in FIG. 2G.

The plug fill 250 may then be removed in a wet etch process via a flow of at least one of ammonium hydroxide, hydrogen peroxide, water, thyroxine 5-deiodinase, nitric acid (HNO3), (trimethylsilyl)dimethylhydrazine (TDMH), or a combination of any of the above. The flow strips away the plug fill 250 at a faster rate than removing other silicon plugs. Etch rates of the plug fill 250 may range between 0.1 and 10000 Angstroms/minute, between 1 and 1000 Angstroms/minute, or between 10 and 100 Angstroms/minute.

After the plug fill 250 is removed, FIG. 2H illustrates that the liner 240 remains. The liner 240 may then be removed via a flow of at least one of: ammonium hydroxide, hydrogen peroxide, water, thyroxine 5-deiodinase, nitric acid (HNO3), (trimethylsilyl)dimethylhydrazine (TDMH), or a combination of any of the above. What remains is the device 200 as shown in FIG. 2I. At this point, manufacture of the device 200 may be complete, or steps may be repeated in order to form additional stacks on top of the device 200.

FIG. 3 illustrates a method 300 for manufacturing a 3-D NAND device in accordance with at least one embodiment of the invention. The method 300 comprises: a dry etch step 310; a liner deposition step 320; a plug fill step 330; a polishing step 340; a stack deposition step 350; a hole etch step 360; and an optional strip step 370. The strip step 370 may not be needed if the hole etch step 360 also removes a liner.

The methods of forming the 3-D NAND device may take place in an ALD reaction chamber, a chemical vapor deposition (CVD) chamber, an epitaxial reaction chamber, a batch reaction chamber, a mini-batch reaction chamber, or a single wafer reaction chamber, for example. The proper reaction chamber may allow for all or a large part of these processes to occur as an in-situ process.

FIG. 4 illustrates a 3-D NAND device 400 made in accordance with at least one embodiment of the invention. The 3-D NAND device 400 comprises a substrate 410, an oxide-nitride layer stack section 420, a source line 430, and a bit-line electrode section 440. The oxide-nitride layer stack section 420 may also comprise a plurality of channel holes.

The particular implementations shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and/or physical couplings between the various elements. Many alternative or additional functional relationship or physical connections may be present in the practical system, and/or may be absent in some embodiments.

It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases.

The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof. 

The invention claimed is:
 1. A method of forming a 3-D NAND device on a substrate, the method comprising: depositing a bilayer structure on a semiconductor substrate, wherein the bilayer structure comprises alternating layers of an oxide layer and a nitride layer; etching a channel hole in the bilayer structure with a first chemical; depositing a liner on a top of the bilayer structure and on a side of the bilayer structure within the channel hole; depositing a plug fill in the channel hole, the plug fill comprising at least one of: a silicon germanium plug or a graded germanium plug; polishing the plug fill to expose the liner on top of the bilayer structure; etching the plug fill with a second chemical; and removing the liner; wherein any of the above steps are repeated to form a desired height of the 3-D NAND device, and wherein the step of depositing the plug fill in the channel hole comprises: depositing a layer of silicon germanium or a graded germanium in the channel hole; etching back a portion of the layer of silicon germanium or a graded germanium in the channel hole; and pinching off a top of the etched back layer of silicon germanium or a graded germanium to create a void in the plug fill, wherein the pinching of the top of the layer encloses the void in the plug fill, a size of the void being controlled by the etching back the portion of the layer.
 2. The method of claim 1, wherein the liner comprises at least one of: germanium oxide; germanium (Ge); silicon germanium (SiGe); germanium nitride (GeN); or pure silicon (Si).
 3. The method of claim 1 wherein the plug fill comprises silicon germanium (SiGe), and wherein a germanium content in the plug fill ranges from 1% to 100%.
 4. The method of claim 1, wherein the pinching of the top of the layer comprises depositing at least one of germanium; silicon; or silicon-germanium alloy.
 5. The method of claim 4, wherein the step of depositing the plug fill in the channel hole comprises flow of a silane precursor, the silane precursor comprising at least one of: silane; disilane; trisilane; chlorosilane; dichlorosilane; trichlorosilane; tetrachlorosilane; neopentasilane; methylsilane; dimethylsilane; trimethylsilane; tetramethylsilane; or a combination of the foregoing.
 6. The method of claim 4, wherein the step of depositing the plug fill in the channel hole comprises flow of a germanium precursor, the germanium precursor comprising at least one of: germane; digermane; dichlorogermane; trichlorogermane; tetrachlorogermane; germanium alkoxide; or a combination of the foregoing.
 7. The method of claim 1, wherein the first chemical comprises at least one of: hydrofluoric acid (HF), hydrochloric acid (HCl), hydrofluoric acid (HF), hydrobromic acid (HBr), or a combination of the foregoing.
 8. The method of claim 1, wherein the second chemical comprises at least one of: hydrogen chloride (HCl); hydrogen fluoride (HF); hydrobromic acid (HBr); ammonium hydroxide; hydrogen peroxide; water; thyroxine 5-deiodinase; nitric acid (HNO₃); (trimethylsilyl)dimethylhydrazine (TDMH); or a combination of any of the above.
 9. The method of claim 1, wherein the step of polishing the plug fill comprises a chemical mechanical polishing (CMP).
 10. The method of claim 1, wherein the step of depositing the plug fill in the channel hole further comprises an in-situ doping with a dopant, the dopant comprising at least one of: germanium (Ge); gallium (Ga); boron (B); phosphorus (P); arsenic (As); or aluminum (Al).
 11. An apparatus for forming a 3-D NAND device, wherein the apparatus is configured to perform the method of claim
 1. 12. The apparatus of claim 11, wherein the apparatus comprises at least one of: a vertical furnace system; a batch reactor system; or a single wafer reactor system.
 13. A method of forming a device on a substrate, the method comprising: depositing a bilayer structure on a substrate; etching a channel hole in the bilayer structure; depositing a liner on a top of the bilayer structure and on a side of the bilayer structure within the channel hole; depositing, over the liner, a plug fill in the channel hole, the plug fill comprising at least one of: a silicon germanium plug or a graded germanium plug; wherein the step of depositing the plug fill in the channel hole comprises: depositing a layer of silicon germanium or a graded germanium in the channel hole; etching back a portion of the layer of silicon germanium or a graded germanium in the channel hole; and pinching off a top of the etched back layer of silicon germanium or a graded germanium to create a void in the plug fill, wherein the pinching of the top of the etched back layer of silicon germanium or a graded germanium encloses the void in the plug fill, and wherein the pinching off the top of the layer comprises deposition of a material differing from the layer in the channel hole and selected from the group consisting of germanium, silicon, and a silicon-germanium alloy.
 14. The method of claim 13, wherein the liner comprises at least one of: germanium oxide; germanium (Ge); silicon germanium (SiGe); germanium nitride (GeN); or pure silicon (Si).
 15. The method of claim 13, wherein the step of depositing the plug fill in the channel hole further comprises an in-situ doping with a dopant, the dopant comprising at least one of: germanium (Ge); gallium (Ga); boron (B); phosphorus (P); arsenic (As); or aluminum (Al).
 16. The method of claim 13, wherein the step of depositing the plug fill in the channel hole comprises flow of a silane precursor, the silane precursor comprising at least one of: silane; disilane; trisilane; chlorosilane; dichlorosilane; trichlorosilane; tetrachlorosilane; neopentasilane; methylsilane; dimethylsilane; trimethylsilane; tetramethylsilane; or a combination of the foregoing.
 17. The method of claim 13, wherein the step of depositing the plug fill in the channel hole comprises flow of a germanium precursor, the germanium precursor comprising at least one of: germane; digermane; dichlorogermane; trichlorogermane; tetrachlorogermane; germanium alkoxide; or a combination of the foregoing.
 18. A method of forming a device on a substrate, the method comprising: depositing a bilayer structure on a substrate, wherein the bilayer structure comprises alternating layers of an oxide layer and a nitride layer; etching a channel hole in the bilayer structure; depositing a liner on a top of the bilayer structure and on a side of the bilayer structure within the channel hole; and depositing a plug fill in the channel hole, the plug fill comprising at least one of: a silicon germanium plug or a graded germanium plug; wherein the liner consists essentially of pure silicon (Si), wherein the step of depositing the plug fill in the channel hole comprises: depositing a layer of silicon germanium or a graded germanium in the channel hole; etching back a portion of the layer of silicon germanium or a graded germanium in the channel hole; and pinching off a top of the etched back layer of silicon germanium or a graded germanium to create a void in the plug fill, wherein the pinching off the top of the etched back layer of silicon germanium or a graded germanium encloses the void in the plug fill.
 19. A method of forming a 3-D NAND device on a substrate, the method comprising: depositing a bilayer structure on a semiconductor substrate, wherein the bilayer structure comprises alternating layers of an oxide layer and a nitride layer; etching a channel hole in the bilayer structure with a first chemical; depositing a liner on a top of the bilayer structure and on a side of the bilayer structure within the channel hole; depositing a plug fill in the channel hole, the plug fill comprising at least one of: a silicon germanium plug or a graded germanium plug; polishing the plug fill to expose the liner on top of the bilayer structure; etching the plug fill with a second chemical; and removing the liner; wherein any of the above steps are repeated to form a desired height of the 3-D NAND device, and wherein the step of depositing the plug fill in the channel hole comprises: depositing a layer of silicon germanium or a graded germanium in the channel hole; etching back a portion of the layer of silicon germanium or a graded germanium in the channel hole; and pinching off a top of the etched back layer of silicon germanium or a graded germanium to create a void in the plug fill, wherein the pinching off the top of the layer encloses the void in the plug fill, a size of the void being controlled at least in part by the depositing a layer of silicon germanium or a graded germanium by varying a deposition rate of the silicon germanium or the graded germanium at least once during deposition of the layer in the channel hole. 